What is the sequence of events when a DSTni-LX boots? How long does it take to boot?

11-Dec-02 Release 1.0
DSTni-LX Bootstrap Notes
This set of informal notes provides information in response to questions about the operation of the DSTni-LX bootstrap.

1)      What happens on power-up or reset and how much time elapsed before the bootstrap
begins loading or starting an application? The bootstrap will perform the following
activities:

a.      Perform a byte-wide checksum over the range of the bootstrap code space
(FF800 through FFFFF for 20-bit mode, FFF800 through FFFFFF for 24-bit 
mode). The expected result of the sum is zero. The topmost byte of the 
address range is the checksum.

b.      Perform a pattern test over the on-chip Static RAM address range (00000 
through 3FFFF). This consists of 6 passes over the range. The first pass 
performs word writes to fill the 128K words with the pattern AAAAh. The 
second pass verifies the AAAAh pattern. The third pass fills the range with 
5555h. The fourth pass verifies the 5555h pattern. The fifth pass fills the range 
with 0000h. The sixth pass verifies the entire on-chip RAM is zero.
The LED0 PIO pin is driven active during the RAM test period.

c.      Copy the initialized data segment from the bootstrap code space to its data 
space located at 00400h through 007FFH. This is done as a word string move 
loop.

d.      Poll serial port 0 for 1 second, testing for the presence of a host computer 
attempting to communicate with the bootstrap. If a valid character sequence is 
received within this time, begin the process to load and execute a binary 
image from the serial port. If the expected character sequence is not received 
within 1 second, proceed to the next bootstrap step.

e.      Check for the presence of the signature (‘FC-1’) in parallel flash (location 
FF7E0 for 20-bit mode, FFF7E0 for 24-bit mode). If signature is present, 
perform a far jump to location FF7E:0000 (20-bit mode) or FFF7:00E0 (24-bit 
mode), starting the application in parallel flash. If signature is not present, 
proceed to the next bootstrap step.

f.      Initialize the SPI device and perform a 264 byte read operation from Page 5 of 
the Atmel serial flash. Check the data for the presence of a valid DSTni binary 
file header. If the header is valid, proceed to load the file from SPI flash to on-
chip RAM. Perform a 16-bit checksum during the load process. If the 
checksum is zero upon completion of the load, jump to start address stored in 
the file header. If a valid header is not found or the checksum fails, proceed to 
the next bootstrap step. The bootstrap runs the SPI channel at 933MHz.

g.      There are no valid boot sources available. Remain in a loop constantly polling 
serial port 0 for a download attempt from a host computer.

We have the following timing measurements:

·       Elapsed time from end of reset to end of internal RAM test: 101ms
·       Elapsed time polling serial port 0: 1000ms
·       Elapsed time from end of RAM test to start of load from SPI flash: 1150ms
·       SPI flash load speed: 115K bytes/sec
·       Worse case (5 wait states) copy speed from parallel flash to RAM using 16-bit string move: 16.6M bytes/sec

Some extra notes:
·       The bootstrap does not attempt to test external RAM.
·       For parallel flash execution, the bootstrap initializes the upper memory 
chip select to the worse case wait-state value, 5 (120ns per cycle). If the 
parallel flash being used can run faster, the application code can, during its 
startup, reprogram UMCS to access parallel flash faster.
[Originally Published On: 12/16/2002 03:39 PM]
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